Ok from the lscpu output you are just a single numa domain per socket.  From the nvidia-smi topo -m it seems to paint that all of the GPUs are on the first socket.  Does that match what you expect on this server?

--
Brian D. Haymore
University of Utah
Center for High Performance Computing
155 South 1452 East RM 405
Salt Lake City, Ut 84112
Phone: 801-558-1150
http://bit.ly/1HO1N2C
From: Dj Merrill <slurm@deej.net>
Sent: Monday, October 19, 2026 11:20 AM
To: Brian Haymore <brian.haymore@utah.edu>; slurm-users <slurm-users@lists.schedmd.com>
Subject: Re: [slurm-users] Jobs not getting assigned the requested GPU card
 
Hi Brian,
Thanks for continuing to help with this.

# lscpu
Architecture:                x86_64
  CPU op-mode(s):            32-bit, 64-bit
  Address sizes:             46 bits physical, 48 bits virtual
  Byte Order:                Little Endian
CPU(s):                      16
  On-line CPU(s) list:       0-15
Vendor ID:                   GenuineIntel
  BIOS Vendor ID:            Intel(R) Corporation
  Model name:                Intel(R) Xeon(R) Gold 5217 CPU @ 3.00GHz
    BIOS Model name:         Intel(R) Xeon(R) Gold 5217 CPU @ 3.00GHz
    CPU family:              6
    Model:                   85
    Thread(s) per core:      1
    Core(s) per socket:      8
    Socket(s):               2
    Stepping:                7
    CPU(s) scaling MHz:      94%
    CPU max MHz:             3700.0000
    CPU min MHz:             1200.0000
    BogoMIPS:                6000.00
    Flags:                   fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pg
                             e mca cmov pat pse36 clflush dts acpi mmx fxsr sse
                             sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm cons
                             tant_tsc art arch_perfmon pebs bts rep_good nopl xt
                             opology nonstop_tsc cpuid aperfmperf pni pclmulqdq
                             dtes64 monitor ds_cpl smx est tm2 ssse3 sdbg fma cx
                             16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe po
                             pcnt tsc_deadline_timer aes xsave avx f16c rdrand l
                             ahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp
                             _l3 intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanc
                             ed fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms inv
                             pcid cqm mpx rdt_a avx512f avx512dq rdseed adx smap
                              clflushopt clwb intel_pt avx512cd avx512bw avx512v
                             l xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_
                             llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln
                              pts pku ospke avx512_vnni md_clear flush_l1d arch_
                             capabilities
Caches (sum of all):         
  L1d:                       512 KiB (16 instances)
  L1i:                       512 KiB (16 instances)
  L2:                        16 MiB (16 instances)
  L3:                        22 MiB (2 instances)
NUMA:                        
  NUMA node(s):              2
  NUMA node0 CPU(s):         0-7
  NUMA node1 CPU(s):         8-15
Vulnerabilities:             
  Gather data sampling:      Mitigation; Microcode
  Indirect target selection: Mitigation; Aligned branch/return thunks
  Itlb multihit:             KVM: Mitigation: VMX unsupported
  L1tf:                      Not affected
  Mds:                       Not affected
  Meltdown:                  Not affected
  Mmio stale data:           Mitigation; Clear CPU buffers; SMT disabled
  Old microcode:             Not affected
  Reg file data sampling:    Not affected
  Retbleed:                  Mitigation; Enhanced IBRS
  Spec rstack overflow:      Not affected
  Spec store bypass:         Mitigation; Speculative Store Bypass disabled via p
                             rctl
  Spectre v1:                Mitigation; usercopy/swapgs barriers and __user poi
                             nter sanitization
  Spectre v2:                Mitigation; Enhanced / Automatic IBRS; IBPB conditi
                             onal; PBRSB-eIBRS SW sequence; BHI SW loop, KVM SW
                             loop
  Srbds:                     Not affected
  Tsa:                       Not affected
  Tsx async abort:           Mitigation; TSX disabled
  Vmscape:                   Mitigation; IBPB before exit to userspace




# dmidecode -t system
# dmidecode 3.6
Getting SMBIOS data from sysfs.
SMBIOS 3.2.1 present.

Handle 0x0001, DMI type 1, 27 bytes
System Information
    Manufacturer: Supermicro
    Product Name: SYS-4029GP-TRT2
    Version: 123456789
    Wake-up Type: Power Switch
    SKU Number: 1A0615D9
    Family: SMC X11


-Dj


On 10/19/26 13:11, Brian Haymore wrote:
The output you shared from 'nvidai-smi topo -m' and the 'slurmd -G' really seems to point that the GPUs are associated to the first socket with cores 0-7.  Could you share the output of 'lscpu' and 'dmidecode -t system' (I'm just after the brand & model info of the server).  I'd like to see what lscpu shows for the numa domains related to the l3cache as socket angle.